The present invention relates to motion detectors, and in particular to integrated circuit shock detectors for disk drives.
A shock detector for hard disk drives senses movement of the disk drive. A traditional implementation is shown in FIG. 1. It uses a piezo transducer 10 to provide an electrical charge proportional to acceleration. This charge is converted into a voltage using the operational amplifier 12 in conjunction with external components: resistor 14, capacitor 16, resistor 18 and capacitor 20. The voltage is subsequently amplified (typically 40 times) using operational amplifier 22 in conjunction with internal resistors 24, 26 and external capacitor 28. Next, it is low-pass filtered using a 2nd order network low pass filter 29 of resistors 30, 32 and capacitors 34, 36 (all internal) with a cut-off frequency of fLP (typically 15 KHz). Finally the signal is amplified again (typically 15 times) using operational amplifier 38 in conjunction with resistors 40, 42 (internal) and capacitor 44 (external).
Capacitors 28 and 44 help to form a 2nd order high-pass response cut-off frequency fHP (typically 60 Hz.). In addition to this, they reduce the DC closed-loop gain of amplifiers 22 and 38 to unity, thus preventing amplification of their DC input-referred offset voltages. This is very important; otherwise, a typical DC offset voltage of 5 mV at the input of amplifier 22 would be amplified to 5 mV×40=200 mV at the output of amplifier 22 and 5 mV×40×15=3V at the output of amplifier 38. With a VDD of 5V and VDD/2 of 2.5V, this is enough to saturate amplifier 38, although amplifier 22 will be able to operate normally.
Finally, the amplified signal (typically a total amplification of 600 times at the output of amplifier 38) is fed into a window comparator composed of comparators 46 and 48 and an OR gate 50. The comparator compares the signal against a threshold window of width 2VR (typically 10% of VDD) about the common reference voltage VDD/2 where VDD is the power supply voltage to the chip. Therefore, a valid movement is detected at OUT whenever the peak value of the amplified signal exceeds VR. For a VDD of 5V, VR=0.25V.
At this point, it is to be noted that any DC offset exceeding a magnitude of VR at the output of amplifier 38 will trip either of the comparators 46 or 48 resulting in a false output even without any signal from transducer 10. With the help of capacitors 28 and 44 it can be ensured that the DC offset voltage at the output of amplifier 38 is no more than the input referred offset of an op-amp (typically 5 mV).
A disadvantage of this circuit is the number of external components. Bringing some external components inside would reduce the number of external components as well as the pin count cost. However, all the external components (resistors 14 and 18, and capacitors 16, 20, 28 and 44) are too large in value to be directly integrated.